Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Type Conversion

  • Type Conversions can convert between integer types or between similar array types.
  • Two arrays are similar if they have the same length and have convertible or identical element types
  • Enumerated types are not convertible

Syntax

  TypeName (Expression)

Where

See Expression

Rules

TypeName must be the name of an integer, floating or array type.

Things to remember

Type conversions are only defined implicitly for closely related types. For other types, you must write explicit conversion functions.

Example

  signal I: Integer;
  signal R: Real;
  ...
  R <= Real(I) * 2.0;
  ...
  type Std_logic_vector is
    array (Natural range <>) of Std_logic;
  type Unsigned is
    array (Natural range <>) of Std_logic;
  -- Std_logic_vector and Unsigned are closely related
  signal S: Std_logic_vector(7 downto 0);
  signal U: Unsigned(7 downto 0);
  ...
  S <= Std_logic_vector(U);
  U <= Unsigned(S);

See Also

Function, Type, Integer, Floating, Array, Qualified Expression